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shanghai belling corp., ltd BL24C128/256 1 BL24C128/bl24c256 128k bits (16,384 x 8) / 256k bits ( 32,768 x 8) t w o-wire serial eeprom features two-wire serial interface v cc = 1.8v to 5.5v bi-directional data transfer protocol internally organized BL24C128, 16,384 x 8 (128k bits) bl24c256, 32,768 x 8 (256k bits) 400 khz (1.8v, 2.7v, 5v) compatibility 64-byte page (128k/256k) write modes partial page writes allowed self-timed write cycle (5 ms max) high-reliability 1 million write cycles guaranteed data retention > 100 years operating temperature: -40 to +85 8-lead pdip, 8-lead sop and 8-lead tssop packages pin configuration description BL24C128/bl24c256 provides 131,072/262, 144 bits of serial ele c trically erasable and programma ble read-only me mor y ( eeprom) organized as 16,384/32,768 words of 8 bits each. the device is optimized for use in many i ndustrial an d commercial applications where low-power and low-voltage operatio ns are esse ntial. the b l24c128/bl24c256 is a v ailable in space-savin g 8-lead pdip, 8-lead sop, and 8-l ead tssop packages a nd is accessed via a two-wire serial interface.
shanghai belling corp., ltd BL24C128/256 2 pin descriptions block diagram
shanghai belling corp., ltd BL24C128/256 3 device/p a g e a d dresse s ( a 1 and a 0 ): the a1 and a0 pins are d e vice address input s that are hard w i re d for the k24c128/k24 c 2 56. four 128k/25 6 k device s may be addressed on a single bus sy s t em (device addressing is d i scussed in detail under the device addressing section). s e r ia l da t a ( s da ) : the sd a pin is b i -directional for serial data transfer. this pin is open-drain d r iven and ma y be w i re -ore d w i th any number of other open-dr ain or open- collector devices. seri a l cloc k (scl): the scl input is used to positive edge clock data into e a ch eeprom de vice and negative edge cl o c k data out of each device. write protect (wp): the k24c128/k 2 4 c 256 has a writ e protect pin th a t provides hard w are data prot ection. the w r ite protect pin allows normal read/ wri t e operat ions w h en connected to ground (gnd). when the write protect pin is connected to vcc , the w r ite protection feature is enabled and operat es as show n in the follow i ng table 2. functional description 1. memory organization 24c1 28, 128 k serial eeprom: the 128k is internally orga n i z ed as 256 p ages of 64 bytes each. random word addressing requires a 14-bit dat a word address. 24c2 56, 256 k serial eeprom: the 256k is internally orga n i z ed as 512 p ages of 64 bytes each. random word addressing requires a 15-bit dat a word address. 2. device operation c l oc k and d a t a transition s : t he sda pi n is n o rmall y pul le d hig h w i th an e x ternal devic e. data o n th e sda pi n ma y c han ge onl y dur ing s c l l o w ti me per iods (s e e f i gur e 1). d a ta chan ges dur ing s c l h i g h p e rio d s w i ll indicate a start or stop condition as defined below . star t co n d ition : a high-to-lo w trans iti on of sda w i th scl hi gh is a start conditio n w h ich must pre c ede a n y other command (see f i gure 2 ) . stop co ndition: a lo w - t o -hi gh transitio n of sda w i th scl hig h is a stop conditi on. after a read seque nce, the stop command w ill place the eeprom in a standby pow er mode (see figure 2) a ckn ow led g e: all addr esses a nd data w o rds are ser i all y tra n smitted to and from th e eeprom in 8-bit w o rds. t he eeprom sends a ?0? to ackno w l e dg e that it has rece i v ed eac h w o rd. t h is happe ns duri ng the ni nth clock c y cl e. standby mode: t he bl24c 128/b l24 c25 6 features a lo w - p o w e r st and b y m ode w h ich is en abl e d : (a) upo n pow er-up and (b) after the receipt of the st op bi t and the completion of any internal operations memory reset: after an interr upti on i n protoc ol, p o w e r loss or s y ste m reset, an y t w o- w i re part c a n be res e t b y follow i ng these steps: 1. clock up to 9 cy cles. 2. look for sda high in each cy cle w h ile scl is high. 3. create a start condition.
shanghai belling corp., ltd BL24C128/256 4 figure 1 . data validity figure 2. s t art and s t op definition figure 3. output acknowledge
shanghai belling corp., ltd BL24C128/256 5 3. device addressing the 128k/256k eeprom devices all require an 8-bit dev ice address word following a start condition to enable the chip for a read or write operation (see figure 4). the device address word consists of a mandatory ?1?, ?0 ? sequence for the first four most significant bits as shown. this is common to all the serial eeprom devices. the 128k/256k uses the three device address bits a1, a0 to allow as many as four devices on the same bus. these bits must compare to their corresponding hardwired input pins. the a1 and a0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. the eighth bit of the device address is the read/write o peration select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device addres s, the eeprom will output a ?0?. if a compare is not made, the chip will return to a standby state. data security: the BL24C128/bl24c256 has a hardware data protection scheme that allows the user to write protect the entire me mory when the wp pin is at vcc. 4. write operations byte write: a write operation requires two 8-bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a ?0? and then clock in the first 8-bit data word. following receipt of the 8-bit data word, the eeprom will output a ?0? and the addressing device, such as a microcontroller, must terminate t he write sequence with a stop condition. at this time the eeprom ent ers an internally timed write cycle, t wr , to the nonvolatile memory. all inputs are disabled during this write cycle an d the eeprom will not respond until the write is complete (see figure 5). page write: the 128k/256k devices are capable of 64-byte page writes. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clock ed in. instead, after the eeprom ackn owledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. the eeprom will respond with a ?0? after each data word received. the microcontroller must terminate the page write sequence with a stop condition (see figure 6). the data word address lower six (128k/256k) bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the word address, internally generat ed, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than 64 data word s are transmitted to the eeprom, the data word address will ?roll over? and previous data will be overwritten. acknowledge polling: once the internally timed write cy cle has started and the eeprom inputs are disabled, acknowledge polling can be initiated. th is involves sending a start condition followed by the device address word. the read/write bit is representa tive of the operation desired. only if the internal write cycle has completed will the eeprom respond with a ?0?, allowing the read or write sequence to continue. 5. read operations read operations are initiated the same way as writ e operations with the exc eption that the read/write select bit in the device address word is set to ?1 ?. there are three read operat ions: current address read, random address read and sequential read.
shanghai belling corp., ltd BL24C128/256 6 c urrent address re ad: the int e rnal d a ta word ad dre s s cou n ter main tains the last addre s s acce ssed during the last re ad or wr ite op eration, incre m ented by one. this addre ss stay s valid betwee n operation s a s long a s th e chip po we r i s maintaine d . t he ad dre s s ?roll over? du rin g re ad i s fro m the la st byte of the la st memory pa ge to the first byte of t he first page. the address ?roll over? du ring write is from the last byte of the current page to the first byte of the same page. once the dev ice ad dre s s with the rea d /write sele ct bi t set to ?1? is clo c ked in an d ackno w led ged by the eeprom, the c u rrent address data word is s e rially c l ock ed out. the mic r oc ontroller does not res p ond with an input ?0? but does generate a following stop condition (see figure 7 ). r and om rea d : a ran d o m re ad req u ire s a ?du m my? byte write se que nce to load i n the data word address. o n ce the d e vice address wo rd and data wo rd add re ss a r e clo c ked i n an d ackn owl edg ed by th e eeprom, the mic r ocontroller mus t gen erate another s t art c o ndition. t he microcontroller now initiates a current address read by sending a dev ice address with t he read/write select bit high. the eeprom ackno w le dge s the device address an d seri ally clo c ks out the dat a wo rd. the microcontroll er doe s no t respond with a ?0? but does generate a following stop condition (see figure 9). sequenti a l rea d : se quential rea d s a r e initiate d by eithe r a cu rre nt add ress read or a ra ndom address rea d . after the micro c o n troll e r receives a da ta word, it respond s with an ackno w led ge. as long as the eeprom receives an acknowl edge, it will c ontinue to i n crement the data word address and seri ally clo c k out sequ enti a l data wo rd s. whe n t he memory ad dress limit is reached, the data wo rd address will ?roll ove r? a nd the seq u ential rea d will contin ue. the sequ ential rea d o peratio n is terminate d when the microco n trolle r d oes not re sp ond with a ?0? but doe s gene rate a followin g stop condition (see figure 10 ) figure 4. d e v i ce address figure 5. by te w r ite figure 6. page w r ite
shanghai belling corp., ltd BL24C128/256 7 figure 7. current address read figure 8. random read figure 9. sequential read
shanghai belling corp., ltd BL24C128/256 8 electrical characteristics
shanghai belling corp., ltd BL24C128/256 9
shanghai belling corp., ltd BL24C128/256 10 ac electrical characteristics
shanghai belling corp., ltd BL24C128/256 11 bus t i ming figure 10. scl: serial cloc k , sda: serial dat a i/o w r ite cy cle t i ming figure 11. scl: serial cloc k , sda: serial data i/o note: 1. the write cycle time t wr is the time from a valid stop c ondition of a write se quence to th e end of the internal clear/write cycle.
shanghai belling corp., ltd BL24C128/256 12 package information pdip outline dimensions note: 1. this dra w ing is for general info rmation only; refer to jedec drawing ms-001, v a riation ba for additional information. 2. dimensions a and l are measured with the p a ckage seated in jedec seating plane gauge gs-3. 3. d, d1 an d e1 dimensions do not include mold flash or pr otrusions. mold fla s h or protrusions shall not exceed 0.010 inch. 4. e and ea measured with the leads constrained to be perpendicular to datum. 5. pointed or rounded lead tip s are preferred to ease insertion. 6. b2 and b3 maxi mum dimensions do not include damba r protrusion s. damba r protrusions shall not exceed 0.010 (0.25 mm).
shanghai belling corp., ltd BL24C128/256 13 jedec soic note: 1. these dr a w ings are for gener a l informatio n only . r e fer to jedec dr a w ing ms-012, v a riation aa for proper dime nsions, toler a nces, datums, etc.
shanghai belling corp., ltd BL24C128/256 14 tssop note: 1. this dr a w ing is for gener a l information only . r e fer to jedec dr a w ing mo-153, v a riation aa, for proper di mensions, toler a nces, datums, etc. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs sha ll not ex ceed 0.15 mm (0.006 in) per side . 3. dimension e1 does not include inter - lead flash or protrusions. inter - lead flash and protrusions shall not ex ceed 0.25 mm (0.010 in) per side. 4. dimension b does not include dambar protrusion. allow a ble dambar protrusion shall be 0.08 mm total in ex cess of the b dimension at maximum material condition. dambar cannot be located on the lower r a dius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h.

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